1. Field of the Invention
The present invention relates to, inter alia, an apparatus, a method and a program for working out a layout design of circuit elements in an integrated circuit.
2. Description of the Related Art
The following description sets forth the inventors' knowledge of related art and problems therein and should not be construed as an admission of knowledge in the prior art.
In semiconductor integrated circuits, such as, e.g., LSI (Large Scale Integrated) circuits, in order to work out a layout design of graphic data corresponding to circuit elements, an integrated circuit design apparatus has been conventionally used (see, e.g., JP2004-234450, A, JP2005-062943, A, and JP2005-267291, A).
In a conventional layout technique, within an integrated circuit design apparatus, the layout is designed so that the area and the wire length of the semiconductor circuit become minimum respectively
In addition to the above, by adding further constraints, such as, pair nature, symmetry nature, or side alignment nature of circuit elements, it is configured that a layout the same as or similar to a layout designed by analog designers is automatically designed.
With this, a more regularly arranged layout is obtained, resulting in a layout result having better circuit characteristics, better device matching properties and better wiring nature, e.g., easy-to-wire.
In a conventional layout technique, however, as to circuit elements with no additional constraint, a regular placement is not always guaranteed. If constraints are given to all of the circuit elements to ensure the regular placement, there is a problem that constraint contradiction occurs and/or constraint adding steps become extremely complicated. Another problem is a difficulty in adding constraints for regularly arranging all of the circuit elements. Especially, these problems can be dominantly found in designing analog integrated circuits various in circuit element size.
Under the circumstances, in the layout automatically created by a conventional semiconductor integrated circuit design apparatus, there are such problems that favorable circuit characteristics cannot be obtained, favorable wiring cannot be easily created, or the obtained layout is not accepted by layout designers.
The description herein of advantages and disadvantages of various features, embodiments, methods, and apparatus disclosed in other publications is in no way intended to limit the present invention. For example, certain features of the preferred embodiments of the invention may be capable of overcoming certain disadvantages and/or providing certain advantages, such as, e.g., disadvantages and/or advantages discussed herein, while retaining some or all of the features, embodiments, methods, and apparatus disclosed therein.